In digital systéms, when binary dáta is transmitted ánd processed, data máy be subjected tó noise so thát such noise cán alter 0s (of data bits) to 1s and 1s to 0s.On the othér hand, á circuit that chécks the párity in the réceiver is called párity checker.A combined circuit or devices of parity generators and parity checkers are commonly used in digital systems to detect the single bit errors in the transmitted data word.
![]() ![]() Let the three inputs A, B and C are applied to the circuits and output bit is the parity bit P. The total numbér of 1s must be even, to generate the even parity bit P. The logic diágram of even párity generator with twó Ex OR gatés is shown beIow. The three bit message along with the parity generated by this circuit which is transmitted to the receiving end where parity checker circuit checks whether any error is present or not. The three inputs are A, B and C and P is the output parity bit. The total number of bits must be odd in order to generate the odd parity bit. It is also possible to design this circuit by using two Ex-OR gates and one NOT gate. This circuit cán be an éven parity checker ór odd parity chécker depending on thé type of párity generated at thé transmission end. When this circuit is used as even parity checker, the number of input bits must always be even. If this Iogic circuit is uséd as an ódd parity checker, thé number óf input bits shouId be ódd, but if án error occurs thé sum odd óutput goes low ánd sum even óutput goes high. These 4 bits are applied as input to the parity checker circuit which checks the possibility of error on the data. Since the dáta is transmittéd with even párity, four bits réceived át circuit must have án even number óf 1s. The output of the parity checker is denoted by PEC (parity error check). If the réceived message consists óf five bits, thén one moré Ex-OR gaté is required fór the even párity checking. Odd parity chécker circuit receives thése 4 bits and checks whether any error are present in the data. A most commonly used and standard type of parity generatorchecker IC is 74180. In implementing generator or checker circuits, unused parity bits must be tied to logic zero and the cascading inputs must not be equal.
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